Reset Sequence - Renesas H8S/2633 Series Hardware Manual

Table 4-3 Types of Reset
Type Conditions for
Transition to Reset
MRES
Power-on reset *
Manual reset Low
4.2.3

Reset Sequence

This LSI enters reset state when the RES pin or MRES pin goes low.
To ensure that this LSI is reset, hold the RES pin or the MRES pin low for at least 20 ms at power-
up. To reset during operation, hold the RES pin or the MRES pin low for at least 20 states.
When the RES pin or the MRES pin goes high after being held low for the necessary time, this
LSI starts reset exception handling as follows.
1. The internal state of the CPU and the registers of the on-chip supporting modules are
initialized, the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR.
2. The reset exception handling vector address is read and transferred to the PC, and program
execution starts from the address indicated by the PC.
Figures 4-2 and 4-3 show examples of the reset sequence.
RES
CPU
Low Initialization Initialization
High Initialization Initialization except for bus controller and I/O
Internal State
Built-in vicinity module
port
*: Don't Care
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