Renesas H8S/2633 Series Hardware Manual page 512

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Port 3 Data Direction Register (P3DDR)
Bit
:
7
P37DDR
Initial value :
0
R/W
:
W
P3DDR is an 8-bit write-dedicated register, which specifies the I/O for each port 3 pin by bit.
Read is disenabled. If a read is carried out, undefined values are read out.
By setting P3DDR to 1, the corresponding port 3 pins become output, and be clearing to 0 they
become input.
P3DDR is initialized to H'00 by a power-on reset and in hardware standby mode. The previous
state is maintained by a manual reset and in software standby mode. SCI is initialized, so the pin
state is determined by the specification of P3DDR and P3DR.
Port 3 Data Register (P3DR)
Bit
:
7
P37DR
Initial value :
0
R/W
:
R/W
P3DR is an 8-bit readable/writable register, which stores the output data of port 3 pins (P35 to
P30).
P3DR is initialized to H'00 by a power-on reset and in hardware standby mode. The previous state
is maintained by a manual reset and in software standby mode.
458
6
5
P36DDR
P35DDR
P34DDR
0
0
W
W
6
5
P36DR
P35DR
0
0
R/W
R/W
4
3
P33DDR
P32DDR
0
0
W
W
4
3
P34DR
P33DR
P32DR
0
0
R/W
R/W
2
1
P31DDR
P30DDR
0
0
W
W
2
1
P31DR
P30DR
0
0
R/W
R/W
R/W
0
0
W
0
0

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