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7.5.8
Wait Control
There are two methods of inserting wait states in DRAM access: (1) insertion of program wait
states, and (2) insertion of pin waits via WAIT pin.
(1) Insertion of Program Wait States
Setting the ASTCR bit of an area set for DRAM to 1 automatically inserts from 0 to 3 wait states,
as set by WCRH and WCRL, between the T
When a program wait is inserted, the write wait function is activated and only the CAS signal is
output only during the T
Figure 7-17 shows example timing for the insertion of program waits.
Address bus
AS
CSn (RAS)
CAS, LCAS
Read
RD
CAS, LCAS
Write
HWR (WE)
Note: ↓ shows timing for WAIT pin sampling.
n= 2 to 5
Figure 7-17 Example Program Wait Insertion Timing (Wait 2 State Insertion)
state when writing.
c2
T
p
ø
Data bus
Data bus
state and T
state.
c1
c2
T
T
T
r
c1
w
RCTS= 0
RCTS= 1
Program
waits
T
T
w
c2
Read data
Write data
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