Register Configuration; Register Descriptions; System Control Register (Syscr) - Renesas H8S/2633 Series Hardware Manual

21.1.2

Register Configuration

The on-chip RAM is controlled by SYSCR. Table 21-1 shows the address and initial value of
SYSCR.
Table 21-1 RAM Register
Name
System control register
Note: * Lower 16 bits of the address.
21.2

Register Descriptions

21.2.1

System Control Register (SYSCR)

Bit : 7
MACS
Initial value : 0
R/W
R/W :
The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. For details of other bits in
SYSCR, see section 3.2.2, System Control Register (SYSCR).
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized when the reset state is released. It is not initialized in software standby mode.
Note: When the DTC* is used, the RAME bit must not be cleared to 0.
* The DTC function is not available in the H8S/2695.
Bit 0
RAME Description
0 On-chip RAM is disabled
1 On-chip RAM is enabled
892
Abbreviation
SYSCR
6 5 4
— INTM1 INTM0
0 0 0
— R/W
R/W
R/W Initial Value
R/W H'01
3 2
NMIEG MRESE
0 0
R/W R/W
Address*
H'FDE5
1 0
— RAME
0 1
— R/W
(Initial value)