Renesas H8S/2633 Series Hardware Manual page 557

• Mode 7
Setting a PFDDR bit to 1 makes the corresponding port F pin PF6 to PF0 an output port, or in
the case of pin PF7, the ø output pin. Clearing the bit to 0 makes the pin an input port.
Port F Data Register (PFDR)
Bit : 7
PF7DR
Initial value : 0
R/W : R/W
PFDR is an 8-bit readable/writable register that stores output data for the port F pins (PF7 to PF0).
PFDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior
state by a manual reset or in software standby mode.
Port F Register (PORTF)
Bit : 7
PF7
Initial value : —*
R/W : R
Note: * Determined by state of pins PF7 to PF0.
PORTF is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port F pins (PF7 to PF0) must always be performed on PFDR.
If a port F read is performed while PFDDR bits are set to 1, the PFDR values are read. If a port F
read is performed while PFDDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORTF contents are determined by the pin
states, as PFDDR and PFDR are initialized. PORTF retains its prior state by a manual reset or in
software standby mode.
6 5
PF6DR PF5DR PF4DR
0 0
R/W R/W
6 5
PF6 PF5
—* —*
R R
4 3
PF3DR PF2DR
0 0
R/W R/W R/W
4 3
PF4 PF3 PF2
—* —* —*
R R
2 1 0
PF1DR PF0DR
0 0 0
R/W R/W
2 1 0
PF1 PF0
—* —*
R R R
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