Block Diagram - Renesas H8S/2633 Series Hardware Manual

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Block Diagram

Figure 9-1 shows a block diagram of the DTC.

The DTC's register information is stored in the on-chip RAM*. A 32-bit bus connects the DTC to

the on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register

information.

Note: * When the DTC is used, the RAME bit in SYSCR must be set to 1.

Interrupt controller

CPU interrupt

DTCERA to DTCERF,

: DTC mode registers A and B

: DTC transfer count registers A and B

: DTC source address register

: DTC destination address register

: DTC enable registers A to F and I

: DTC vector register

Figure 9-1 Block Diagram of DTC

Internal address bus

Internal data bus