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14.3
Bus Master Interface
DACNT, DADRA, and DADRB are 16-bit registers. The data bus linking the bus master and the
on-chip supporting modules, however, is only 8 bits wide. When the bus master accesses these
registers, it therefore uses an 8-bit temporary register (TEMP).
These registers are written and read as follows (taking the example of the CPU interface).
• Write
When the upper byte is written, the upper-byte write data is stored in TEMP. Next, when the
lower byte is written, the lower-byte write data and TEMP value are combined, and the
combined 16-bit value is written in the register.
• Read
When the upper byte is read, the upper-byte value is transferred to the CPU and the lower-byte
value is transferred to TEMP. Next, when the lower byte is read, the lower-byte value in
TEMP is transferred to the CPU.
These registers should always be accessed 16 bits at a time (by word access or two consecutive
byte accesses), and the upper byte should always be accessed before the lower byte. Correct data
will not be transferred if only the upper byte or only the lower byte is accessed.
Figure 14-2 shows the data flow for access to DACNT. The other registers are accessed similarly.
Example 1: Write to DACNT
MOV.W R0, @DACNT
Example 2: Read DADRA
MOV.W @DADRA, R0
Table 14-3 Read and Write Access Methods for 16-Bit Registers
Register Name
DADRA and DADRB
DACNT
Notes: Yes: Permitted type of access. Word access includes successive byte accesses to the
upper byte (first) and lower byte (second).
×:
This type of access may give incorrect results.
; Write R0 contents to DACNT
; Copy contents of DADRA to R0
Read
Word
Byte
Yes
Yes
×
Yes
Write
Word
Byte
×
Yes
×
Yes
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