Renesas H8S/2633 Series Hardware Manual page 19

Section
18.3.9 Noise Canceler 
18.4 Usage Notes
19.1.2 Block Diagram 860
19.2.2 A/D
Control/Status Register
(ADCSR)
19.2.3 A/D Control
Register (ADCR)
19.5 Interrupts
Section 20 D/A
Converter
21.1 Overview
21.2.1 System Control
Register (SYSCR)
Page Item
Figure 18-14 Flowchart for
Master Transmit Mode
(Example)
Figure 18-15 Flowchart for
Master Receive Mode
(Example)
850 Table 18-7 Permissible SCL
Rise Time (t
851 Table 18-8 I
(with Maximum Influence of
t /t )
Sr Sf
854 to 857 • Notes on IRIC Flag
Clearance when Using Wait
Function
• Notes on ICDR Reads and
ICCR Access in Slave
Transmit Mode
• Notes on TRS Bit Setting in
Slave Mode
• Notes on ICDR Reads in
Transmit Mode and ICDR
Writes in Receive Mode
• Notes on ACKE Bit and TRS
Bit in Slave Mode
Figure 19-1 Block Diagram
of A/D Converter
864 Bit 7—A/D End Flag (ADF)
867 Bits 7 and 6—Timer Trigger
Select 1 and 0 (TRGS1,
TRGS0)
876
Table 19-6 A/D Converter
Interrupt Source
883
891 to 893
892
Description
Deleted
ø = 28 MHz portion added to
) Values time indication [ns]
Sr
2
C Bus Timing ø = 28 MHz portion added to
time indication [ns] and
values amended
Newly added
Note * added
Title amended
H8S/2633R added after
H8S/2633 and H8S/2695
added after H8S/2631
Note * added
11