Table of Contents
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Section
16.2.8 Bit Rate
Register (BRR)
16.2.10 IrDA Control
Register (IrCR)
16.3.2 Operation in
Asynchronous Mode
16.3.3 Multiprocessor
Communication
Function
16.3.4 Operation in
Clocked Synchronous
Mode
16.4 SCI Interrupts
16.5 Usage Notes
Page
Item
713
Table 16-3 BRR Settings
for Various Bit Rates
(Asynchronous Mode)
714
Table 16-4 BRR Settings for
Various Bit Rates (Clocked
Synchronous Mode)
716
Table 16-5 Maximum Bit
Rate for Each Frequency
(Asynchronous Mode)
717
Table 16-6 Maximum Bit
Rate with External Clock Input
(Asynchronous Mode)
718
Table 16-7 Maximum Bit
Rate with External Clock Input
(Clocked Synchronous Mode)
720
730
Figure 16-5 Sample Serial
Transmission Flowchart
739
Figure 16-10 Sample
Multiprocessor Serial
Transmission Flowchart
747
Figure 16-16 Sample Serial
Transmission Flowchart
750
Figure 16-18 Sample Serial
Reception Flowchart
752
Figure 16-20 Sample
Flowchart of Simultaneous
Serial Transmit and Receive
Operations
756
757
Table 16-13 SCI Interrupt
Sources
761
Restrictions on Use of DMAC
or DTC
762
Figure 16-25 Sample
Flowchart for Mode Transition
during Transmission
Description
28 MHz bit rate added
Note added
Note * added
Note *1 added
Note * added
9
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