Renesas H8S/2633 Series Hardware Manual page 15

Section
Section 12
Programmable Pulse
Generator (PPG)
(This function is not
available in the
H8S/2695)
12.2.1 Next Data
Enable Registers H and
L (NDERH, NDERL)
Section 13 8-Bit
Timers (TMR)
(This function is not
available in the
H8S/2695)
13.3.5 Operation with
Cascaded Connection
13.4.1 Interrupt
Sources and DTC
Activation
(The H8S/2695 does
not have a DTC
function or an 8-bit
timer)
Section 14 14-Bit
PWM D/A
(This function is not
available in the
H8S/2695)
Section 15 Watchdog
Timer
(WDT1 is not available
in the H8S/2695)
15.1.1 Features
15.1.2 Block Diagram 673
15.1.3 Pin
Configuration
15.2.2 Timer
Control/Status Register
(TCSR)
Page Item
603
608 NDERL Bits 7 to 0—Next Data
Enable 7 to 0 (NDER7 to
NDER0)
629
645
646
655
671
671
Figure 15-1 (b) Block Diagram
of WDT1
674 Table 15-1 WDT Pin
675 TCSR1
676 Bit 6—Timer Mode Select
(WT/IT)
Bit 7—Overflow Flag (OVF)
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