Renesas H8S/2633 Series Hardware Manual page 910

• Notes on TRS Bit Setting in Slave Mode
From the detection of the rising edge of the 9th clock cycle or of a stop condition to when the
rising edge of the next SCL pin signal is detected (the period indicated as (a) in figure 18-26)
in the slave mode of the I
effective immediately.
However, at other times (indicated as (b) in figure 18-26) the value set in the TRS bit is put on
hold until the next rising edge of the 9th clock cycle or stop condition is detected, rather than
taking effect immediately.
This results in the actual internal value of the TRS bit remaining 1 (transmit mode) and no
acknowledge bit being sent at the 9th clock cycle address receive completion in the case of an
address receive operation following a restart condition input with no stop condition
intervening.
When receiving an address in the slave mode, clear the TRS bit to 0 during the period
indicated as (a) in figure 18-26.
To cancel the holding of the SCL bit low by the wait function in the slave mode, clear the TRS
bit to 0 and then perform a dummy read of the ICDR register.
(a)
SDA
SCL
8 9
TRS
Data transmission
TRS bit set
Detection of 9th clock
cycle rising edge
Figure 18-26 TRS Bit Setting Timing in Slave Mode
856
2
C bus interface, the value set in the TRS bit in the ICCR register is
Restart condition
1 2
TRS bit setting hold time
ICDR dummy read
(b)
3 4 5 6
Address reception
A
7 8 9
Detection of 9th clock
cycle rising edge