Renesas H8S/2633 Series Hardware Manual page 268

This LSI
(address shift set to 9 bits)
214
CS (RAS)
CAS
LCAS
HWR (WE)
A9
A8
A7
A6
A5
A4
A3
A2
A1
D15 to D0
Figure 7-20 High-speed Page Mode DRAM
2CAS 4-Mbit DRAM
256KB × 16-bit configuration
9-bit column address
RAS
UCAS
LCAS
WE
A8
A7
A6
(Row address input: A8 to A0)
(Column address input: A8 to A0)
A5
A4
A3
A2
A1
A0
D15 to D0
OE