Renesas H8S/2633 Series Hardware Manual page 903

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Table of Contents

Table 18-6 I

C Bus Timing (SCL and SDA Output)

SCL output cycle time

SCL output high pulse width

SCL output low pulse width

SDA output bus free time

Start condition output hold time

Retransmission start condition output

Stop condition output setup time

Data output setup time (master)

Data output setup time (slave)

Data output hold time

when IICX is 0, 12t

• SCL and SDA input is sampled in synchronization with the internal clock. The AC timing

therefore depends on the system clock cycle t

25 and 26, Electrical Characteristics. Note that the I

will not be met with a system clock frequency of less than 5 MHz.

C bus interface specification for the SCL rise time t

speed mode). In master mode, the I

one bit at a time during communication. If t

the time determined by the input clock of the I

extended. The SCL rise time is determined by the pull-up resistance and load capacitance of

the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance

and load capacitance so that the SCL rise time does not exceed the values given in the table

, as shown in tables 25-10 and 26-10 in section

C bus interface monitors the SCL line and synchronizes

(the time for SCL to go from low to V

C bus interface, the high period of SCL is

Output Timing

C bus interface AC timing specifications

is under 1000 ns (300 ns for high-

Figure 25-33,

figure 26-33