Table of Contents
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Section
21.4 Usage Notes
22.1 Overview
22.1.2 Register
Configuration
22.3 Operation
22.11 Flash Memory
Programmer Mode
22.11.1 Socket
Adapter Pin
Correspondence
Diagram
Section 23A Clock
Pulse Generator
(H8S/2633, H8S/2632,
H8S/2631, H8S/2633F)
23A.2.1 System Clock
Control Register
(SCKCR)
Section 23B Clock
Pulse Generator
(H8S/2633R,
H8S/2695)
24.1 Overview
24.1.1 Register
Configuration
12
Page
Item
893
When Using the DTC
895
898
Table 22-3 Operating Modes
and ROM (Mask ROM Version)
938
Table 22-13 Programmer
Mode Pin Settings
939
Figure 22-18 Socket Adapter
Pin Correspondence Diagram
959
960
Bit 7—ø Clock Output Disable
(PSTOP)
971 to 981
983
984
Table 24-1 LSI Internal States
in Each Mode
985
Figure 24-1(a) Mode
Transition Diagram (H8S/2633
Series, H8S/2633R)
986
Figure 24-1(b) Mode
Transition Diagram (H8S/2695)
987
Table 24.2(a) Power-Down
Mode Transition Conditions
(H8S/2633 Series, H8S/2633R)
Table 24.2(b) Power-Down
Mode Transition Conditions
(H8S/2695)
988
Table 24-3 Power-Down
Mode Registers
Description
Note * added
Description amended
BCRL amended to MDCR
Note * description amended
Note * added
Some pin names of
H8S/2633 amended
Notes *1 and *2 added
Title amended
Direct transition added to
software standby mode and
watch mode in description
Newly added
Note * added
Notes *4 and *5 added,
Note *6 description amended
H8S/2633R added
Newly added
H8S/2633R added
Newly added
Note * added
Note *2 added
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