Renesas H8S/2633 Series Hardware Manual page 59

Item Specification
Operating modes Four MCU operating modes
Mode
4
5
6
7
Clock pulse H8S/2633, H8S/2632, H8S/2631
generator •
•
H8S/2633R, H8S/2695
•
•
•
Packages
•
•
2
I C bus interface
(IIC) * 2 channels
•
(optional)
•
•
Note: * This function is not available in the H8S/2695.
CPU
Operating
Mode Description
Advanced On-chip ROM disabled
expansion mode
On-chip ROM disabled
expansion mode
On-chip ROM enabled
expansion mode
Single-chip mode
On-chip PLL circuit (×1, ×2, ×4)
Input clock frequency: 2 to 25 MHz
On-chip PLL circuit (×1, ×2, ×4) : 2 to 25 MHz
(×2, ×4)
Input clock frequency: 2 to 25 MHz
120-pin plastic TQFP (TFP-120)
128-pin plastic QFP (FP-128B)
2
Conforms to I C bus interface type advocated by Philips
Single master mode/slave mode
Possible to determine arbitration lost conditions
Supports two slave addresses
On-Chip Initial
ROM Value
Disabled 16 bits
Disabled 8 bits
Enabled 8 bits
Enabled —
: 25 to 28 MHz
External Data Bus
Maximum
Value
16 bits
16 bits
16 bits
—
5