Block Diagram - Renesas H8S/2633 Series Hardware Manual

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Table of Contents

Block Diagram

Figure 14-1 shows a block diagram of the PWM D/A module.

Clock selection

Control logic

PWM D/A control register ( 6 bits)

DADRA: PWM D/A data register A (15 bits)

DADRB: PWM D/A data register B (15 bits)

DACNT: PWM D/A counter (14 bits)

Internal clock

compare-match A

Fine-adjustment

pulse addition A

compare-match B

Fine-adjustment

pulse addition B

Basic cycle overflow

Figure 14-1 PWM D/A Block Diagram

Internal data bus

Bus interface

Module data bus