Pin Configuration; Register Configuration - Renesas H8S/2633 Series Hardware Manual

15.1.3

Pin Configuration

Table 15-1 describes the WDT output pin.
Table 15-1 WDT Pin
Name
Watchdog timer overflow
Buzzer output
Note: * This function is not available in the H8S/2695.
15.1.4

Register Configuration

Table 15-2 summarizes the WDT register configuration. These registers control clock selection,
WDT mode switching, and the reset signal.
Table 15-2 WDT Registers
Channel Name
0 Timer control/status register 0 TCSR0
Timer counter 0
Reset control/status register
1 Timer control/status register 1 TCSR1
Timer counter 1
All Pin function control register
Notes: *1 Lower 16 bits of the address.
*2 For details of write operations, see section 15.2.5, Notes on Register Access.
*3 Only a write of 0 is permitted to bit 7, to clear the flag.
674
Symbol I/O
WDTOVF
Output
BUZZ *
Output
Abbreviation R/W
TCNT0
RSTCSR
TCNT1
PFCR
Function
Outputs counter overflow signal in watchdog
timer mode
Outputs clock selected by watchdog timer
(WDT1)
Initial Value Write*
3
R/(W)* H'18
R/W H'00
3
R/(W)* H'1F
3
R/(W)* H'00
R/W H'00
R/W H'0D/H'00
1
Address*
2
Read
H'FF74 H'FF74
H'FF74 H'FF75
H'FF76 H'FF77
H'FFA2 H'FFA2
H'FFA2 H'FFA3
H'FDEB