Pin Configuration - Renesas H8S/2633 Series Hardware Manual

7.1.3

Pin Configuration

Table 7-1 summarizes the pins of the bus controller.
Table 7-1 Bus Controller Pins
Name Symbol
AS
Address strobe
RD
Read
HWR
High write/
write enable*
LWR
Low write
CS0
Chip select 0
CS1
Chip select 1
CS2
Chip select 2/row
address strobe 2*
CS3/OE *
Chip select 3/row
address strobe 3*
CS4
Chip select 4/row
address strobe 4*
CS5
Chip select 5/row
address strobe 5*
CS6
Chip select 6
CS7
Chip select 7
CAS *
Upper column
address strobe*
LCAS *
Lower column
strobe*
Note: * This function is not available in the H8S/2695.
168
I/O Function
Output Strobe signal indicating that address output on address
bus is enabled.
Output Strobe signal indicating that external space is being
read.
Output Strobe signal indicating that external space is to be
written, and upper half (D15 to D8) of data bus is
enabled. 2CAS method DRAM with enable signal*.
Output Strobe signal indicating that external space is to be
written, and lower half (D7 to D0) of data bus is enabled.
Output Strobe signal showing selection of area 0
Output Strobe signal showing selection of area 1
Output Strobe signal showing selection of area 2.
When area 2 is allocated to DRAM space, this is the row
address strobe signal for DRAM*.
When areas 2 to 5 are contiguous DRAM space, this is
the row address strobe signal for DRAM*.
Output Strobe signal showing selection of area 3.
When area 3 is allocated to DRAM space, this is the row
address strobe signal for DRAM*.
When only area 2 is allocated to DRAM space, or when
areas 2 to 5 are contiguous DRAM space, this is output
enable signal*.
Output Strobe signal showing selection of area 4.
When area 4 is allocated to DRAM space, this is the row
address strobe signal for DRAM*.
Output Strobe signal showing selection of area 5.
When area 5 is allocated to DRAM space, this is the row
address strobe signal for DRAM*.
Output Strobe signal showing selection of area 6
Output Strobe signal showing selection of area 7
Output 2 CAS method DRAM upper column address strobe
signal*
Output DRAM lower column address strobe signal*