Renesas H8S/2633 Series Hardware Manual page 37

7.5.4 Data Bus .............................................................................................................. 207
7.5.5 DRAM Interface Pins .......................................................................................... 208
7.5.6 Basic Timing ....................................................................................................... 208
7.5.7 Precharge State Control....................................................................................... 210
7.5.8 Wait Control ........................................................................................................ 211
7.5.9 Byte Access Control ............................................................................................ 213
7.5.10 Burst Operation ................................................................................................... 215
7.5.11 Refresh Control ................................................................................................... 219
7.6 DMAC Single Address Mode and DRAM Interface
(This function is not available in the H8S/2695).............................................................. 223
7.6.1 DDS=1................................................................................................................. 223
7.6.2 DDS=0................................................................................................................. 224
7.7 Burst ROM Interface ........................................................................................................ 225
7.7.1 Overview ............................................................................................................. 225
7.7.2 Basic Timing ....................................................................................................... 225
7.7.3 Wait Control ........................................................................................................ 227
7.8 Idle Cycle.......................................................................................................................... 228
7.8.1 Operation ............................................................................................................. 228
7.8.2 Pin States in Idle Cycle ....................................................................................... 232
7.9 Write Data Buffer Function .............................................................................................. 233
7.10 Bus Release....................................................................................................................... 234
7.10.1 Overview ............................................................................................................. 234
7.10.2 Operation ............................................................................................................. 234
7.10.3 Pin States in External Bus Released State........................................................... 235
7.10.4 Transition Timing................................................................................................ 236
7.10.5 Notes.................................................................................................................... 237
7.11 Bus Arbitration
(DMAC and DTC functions are not available in the H8S/2695) ..................................... 238
7.11.1 Overview ............................................................................................................. 238
7.11.2 Operation ............................................................................................................. 238
7.11.3 Bus Transfer Timing ........................................................................................... 239
7.12 Resets and the Bus Controller........................................................................................... 239
Section 8 DMA Controller (DMAC)
(This function is not available in the H8S/2695)
8.1 Overview........................................................................................................................... 241
8.1.1 Features ............................................................................................................... 241
8.1.2 Block Diagram..................................................................................................... 242
8.1.3 Overview of Functions ........................................................................................ 243
8.1.4 Pin Configuration ................................................................................................ 245
8.1.5 Register Configuration ........................................................................................ 246
8.2 Register Descriptions (1) (Short Address Mode) ............................................................. 247
8.2.1 Memory Address Registers (MAR)..................................................................... 248
................................. 241
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