Pin Function Control Register (Pfcr) - Renesas H8S/2633 Series Hardware Manual

Bit 5—Reset Select (RSTS): Selects the type of internal reset generated if TCNT overflows
during watchdog timer operation.
For details of the types of reset, see section 4, Exception Handling.
Bit 5
RSTS Description
0 Power-on reset
1 Manual reset
Bits 4 to 0—Reserved: These bits are always read as 1 and cannot be modified.
15.2.4

Pin Function Control Register (PFCR)

Bit :
CSS07
Initial value :
R/W : R/W
Note: * This function is not available in the H8S/2695.
PFCR is an 8-bit readable/writable register that performs address output control in external
expanded mode.
Only bit 5 is described here. For details of the other bits, see section 7.2.6, Pin Function Control
Register (PFCR).
Bit 5—BUZZ Output Enable (BUZZE): Enables or disables BUZZ output from the PF1 pin.
The WDT1 input clock selected with bits PSS and CKS2 to CKS0 is output as the BUZZ signal.
Bit 5
BUZZE Description
0 Functions as PF1 I/O pin
1 Functions as BUZZ output pin
Note: In the case of the H8S/2695, only 0 should be written to the BUZZ bit.
7 6 5
BUZZE *
CSS36
0 0 0
R/W R/W
4 3
LCASS AE3 AE2
0 1/0
R/W R/W R/W
(Initial value)
2 1 0
AE1 AE0
1/0 0 1/0
R/W R/W
(Initial value)
681