Renesas H8S/2633 Series Hardware Manual page 739

TCNT count
H'FF
H'00
WT/IT=1
TME=1
WDTOVF signal
Internal reset signal * 1
Legend
WT/IT : Timer mode select bit
TME : Timer enable bit
Notes: *1 The internal reset signal is generated only if the RSTE bit is set to 1.
*2 130 states when the RSTE bit is cleared to 0.
Figure 15-4 (a) WDT0 Watchdog Timer Operation
TCNT value
H'FF
H'00
WT/IT= 1
TME= 1
Internal
reset signal
Legend
WT/IT : Timer Mode Select bit
TME : Timer Enable bit
Note: * The WOVF bit is set to 1 and then cleared to 0 by an internal reset.
Figure 15-4 (b) WDT1 Operation in Watchdog Timer Mode
H'00 written
WDTOVF and
to TCNT
internal reset are
generated
Overflow
Write H'00
to TCNT
Occurrence
of internal reset
Overflow
WOVF=1 WT/IT=1
TME=1
132 states * 2
518 states
WT/IT= 1
WOVF= 1*
TME= 1
515/516 states
Time
H'00 written
to TCNT
Time
Write H'00
to TCNT
685