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Master receive mode
Set ACKB = 0 (ICSR)
Clear IRIC flag in ICCR
Set WAIT = 1 (ICMR)
Read IRIC flag in ICCR
No
No
Clear IRIC flag in ICCR
Set ACKB = 1 (ICSR)
1 clock cycle wait state
Clear IRIC flag in ICCR
Read IRIC flag in ICCR
No
Clear IRIC flag in ICCR
Set WAIT = 0 (ICMR)
Clear IRIC flag in ICCR
Figure 18-10 Flowchart for Master Receive Mode (Receiving Multiple Bytes) (WAIT = 1)
834
Set TRS = 0 (ICCR)
Read ICDR
IRIC = 1?
Yes
IRTR = 1?
Yes
Yes
Final receive?
No
Read ICDR
Set TRS = 1 (ICCR)
Read ICDR
IRIC = 1?
Yes
Yes
IRTR = 1?
No
Read ICDR
Write BBSY = 0
and SCP = 0 (ICCR)
End
[1] Set to receive mode.
[2] Receive start, dummy read.
[3] Receive wait state (IRIC set at falling edge of 8th clock cycle)
or
Wait for end of reception of 1 byte (IRIC set at rising edge
of 9th clock cycle).
[4] Data receive completed judgment.
[5] Read receive data.
[6] Clear IRIC flag (cancel wait state).
[7] Set acknowledge data for final receive.
[8] Wait time until TRS setting.
[9] Set TRS to generate stop condition.
[10] Read receive data.
[11] Clear IRIC flag (cancel wait state).
[12] Receive wait state (IRIC set at falling edge of 8th clock cycle)
or
Wait for end of reception of 1 byte (IRIC set at rising edge
of 9th clock cycle).
[13] Data receive completed judgment.
[14] Clear IRIC flag (cancel wait state).
[15] Cancel wait mode
Clear IRIC flag. (IRIC flag should be cleared when WAIT = 0.)
[16] Read final receive data.
[17] Generate stop condition.
(Example)
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