Renesas H8S/2633 Series Hardware Manual page 206

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If DTC carries out the designate number of data transfers and the transfer counter reads 0, after

DTC data transfer, the DTCE bit is also cleared to 0, and a CPU interrupt requested.

(2) Determination of Priority: The DTC activation source is selected in accordance with the

default priority order, and is not affected by mask or priority levels. See section 8.6, Interrupts,

and section 9.3.3, DTC Vector Table for the respective priority.

(3) Operation Order: If the same interrupt is selected as a DTC activation source and a CPU

interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception

If the same interrupt is selected as the DMAC activation factor and as the DTC activation factor or

CPU interrupt factor, these operate independently. They operate in accordance with the respective

operating states and bus priorities.

Table 5-11 shows the interrupt factor clear control and selection of interrupt factors by

specification of the DTA bit of DMAC's DMABCR, DTC's DTCERA to DTCERF, DTCERI's

DTCE bits, and the DISEL bit of DTC's MRB.

Table 5-11 Interrupt Source Selection and Clearing Control

: The relevant interrupt is used. Interrupt source clearing is performed.

(The CPU should clear the source flag in the interrupt handling routine.)

: The relevant interrupt is used. The interrupt source is not cleared.

X : The relevant bit cannot be used.

Note: *1 This function is not available in the H8S/2695.

(4) Notes on Use: SCI and A/D converter interrupt sources are cleared when the DMAC * or

DTC * reads or writes to the prescribed register, and are not dependent upon the DTA * , DTCE * ,

and DISEL * bits.

Note: * This function is not available in the H8S/2695.

Interrupt Source Selection/Clearing Control