Renesas H8S/2633 Series Hardware Manual page 723

2. OS = 1 (DADR corresponds to T
a. CFS = 0 [base cycle = resolution (T) × 64]
t
f1
t
H1
t = t = t = · · · = t
f1 f2 f3
t + t + t + · · · + t
H1 H2 H3
b. CFS = 1 [base cycle = resolution (T) × 256]
t
f1
t
H1
t = t = t = · · · = t
f1 f2 f3
t + t + t + · · · + t
H1 H2 H3
)
H
1 conversion cycle
t
f2
t t
H2 H3
= T × 64
= t
f255 f256
+ t = T
H255 H256 H
Figure 14-4 (3) Output Waveform
1 conversion cycle
t
f2
t t
H2 H3
= T × 256
= t
f63 f64
+ t = T
H63 H64 H
Figure 14-4 (4) Output Waveform
t
f255
t t
H255 H256
t
f63
t t
H63 H64
t
f256
t
f64
669