Renesas H8S/2633 Series Hardware Manual page 664

Address H'FE2D
Bit : 7
NDR7
Initial value : 0
R/W : R/W
Address H'FE2F
Bit : 7
—
Initial value : 1
R/W : —
Different Triggers for Pulse Output Groups: If pulse output groups 2 and 3 are triggered by
different compare match events, the address of the upper 4 bits in NDRH (group 3) is H'FE2C and
the address of the lower 4 bits (group 2) is H'FE2E. Bits 3 to 0 of address H'FE2C and bits 7 to 4
of address H'FE2E are reserved bits that cannot be modified and are always read as 1.
Address H'FE2C
Bit : 7
NDR15
Initial value : 0
R/W : R/W
Address H'FE2E
Bit : 7
—
Initial value : 1
R/W : —
If pulse output groups 0 and 1 are triggered by different compare match event, the address of the
upper 4 bits in NDRL (group 1) is H'FE2D and the address of the lower 4 bits (group 0) is
H'FE2F. Bits 3 to 0 of address H'FE2D and bits 7 to 4 of address H'FE2F are reserved bits that
cannot be modified and are always read as 1. However, the H8S/2633 Series has no output pins
corresponding to pulse output groups 0 and 1.
610
6 5
NDR6 NDR5
0 0
R/W R/W
6 5
— —
1 1
— —
6 5
NDR14 NDR13 NDR12
0 0
R/W R/W
6 5
— —
1 1
— —
4 3
NDR4 NDR3 NDR2
0 0
R/W R/W
4 3
— —
1 1
— —
4 3
—
0 1
R/W —
4 3
— NDR11 NDR10
1 0
— R/W
2 1
NDR1 NDR0
0 0
R/W R/W R/W
2 1
— —
1 1
— —
2 1
— —
1 1
— —
2 1
NDR9 NDR8
0 0
R/W R/W R/W
0
0
0
—
1
—
0
—
1
—
0
0