Renesas H8S/2633 Series Hardware Manual page 251

8-Bit 3-State Access Space: Figure 7-7 shows the bus timing for an 8-bit 3-state access space.
When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used.
The LWR pin is fixed high. Wait states can be inserted.
Address bus
D15 to D8
Read
D7 to D0
Write
D15 to D8
D7 to D0
Note: n = 0 to 7
Figure 7-7 Bus Timing for 8-Bit 3-State Access Space
T
1
ø
CSn
AS
RD
HWR
LWR
Bus cycle
T
2
High
Valid
High impedance
T
3
Valid
Invalid
197