Basic Timing - Renesas H8S/2633 Series Hardware Manual

7.4.4

Basic Timing

8-Bit 2-State Access Space: Figure 7-6 shows the bus timing for an 8-bit 2-state access space.
When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used.
The LWR pin is fixed high. Wait states cannot be inserted.
Read
Write
Note: n = 0 to 7
Figure 7-6 Bus Timing for 8-Bit 2-State Access Space
196
ø
Address bus
CSn
AS
RD
D15 to D8
D7 to D0
HWR
LWR
D15 to D8
D7 to D0
Bus cycle
T T
1 2
Valid
Invalid
High
Valid
High impedance