Operation Using The Dtc - Renesas H8S/2633 Series Hardware Manual

18.3.8

Operation Using the DTC*

2
The I C bus format provides for selection of the slave device and transfer direction by means of
the slave address and the R/W bit, confirmation of reception with the acknowledge bit, indication
of the last frame, and so on. Therefore, continuous data transfer using the DTC* must be carried
out in conjunction with CPU processing by means of interrupts.
Table 18-5 shows some examples of processing using the DTC*. These examples assume that the
number of transfer data bytes is known in slave mode.
Note: * The DTC function is not available in the H8S/2695.
Table 18-5 Examples of Operation Using the DTC *
Master Transmit
Item Mode
Slave address + Transmission by
R/W bit DTC* (ICDR write)
transmission/
reception
Dummy data —
read
Actual data Transmission by
transmission/ DTC* (ICDR write)
reception
Dummy data —
(H'FF) write
Last frame Not necessary
processing
Transfer request 1st time: Clearing
processing after by CPU
last frame
2nd time: End
processing
condition issuance
by CPU
Setting of Transmission:
number of DTC* Actual data count
transfer data + 1 (+1 equivalent
frames to slave address +
R/W bits)
Note: * The DTC function is not available in the H8S/2695.
Master Receive Slave Transmit
Mode Mode
Transmission by Reception by
CPU (ICDR write) CPU (ICDR read)
Processing by —
CPU (ICDR read)
Reception by Transmission by
DTC* (ICDR read) DTC* (ICDR write)
— Processing by
DTC* (ICDR write)
Reception by Not necessary
CPU (ICDR read)
Not necessary Automatic clearing
on detection of end
condition during
transmission of
dummy data (H'FF)
Reception: Actual Transmission:
data count Actual data count
+ 1 (+1 equivalent
to dummy data
(H'FF))
Slave Receive
Mode
Reception by CPU
(ICDR read)
—
Reception by DTC*
(ICDR read)
—
Reception by CPU
(ICDR read)
Not necessary
Reception: Actual
data count
843