Block Diagram - Renesas H8S/2633 Series Hardware Manual

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Block Diagram

Figure 7-1 shows a block diagram of the bus controller.

External bus control signals

External DRAM

control signal

ABWCR : Bus width control register

: Access state control register

: Bus control register H

: Bus control register L

: Wait control register H

: Wait control register L

Note: * This function is not available in the H8S/2695.

Area decoder

DRAM controller

Figure 7-1 Block Diagram of Bus Controller

CPU bus request signal

DTC * bus request signal

DMAC * bus request signal

CPU bus acknowledge signal

DTC * bus acknowledge signal

DMAC * bus acknowledge signal

: Memory control register

: DRAM control register

: Refresh timer counter

: Refresh time constand register

Internal control

Bus mode signal