Renesas H8S/2633 Series Hardware Manual page 652

Contention between TGR Write and Input Capture: If the input capture signal is generated in
the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to
TGR is not performed.
Figure 11-54 shows the timing in this case.
ø
Address
Write signal
Input capture
signal
TCNT
TGR
Figure 11-54 Contention between TGR Write and Input Capture
598
TGR write cycle
T1 T2
TGR address
M
M