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10B.10.2 Register Configuration
Table 10B-16 shows the port D register configuration.
Table 10B-16 Port D Registers
Name
Port D data direction register
Port D data register
Port D register
Port D MOS pull-up control register
Note: * Lower 16 bits of the address.
Port D Data Direction Register (PDDDR)
Bit
:
7
PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR
Initial value :
0
R/W
:
W
PDDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port D. PDDDR cannot be read; if it is, an undefined value will be read.
PDDDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its
prior state by a manual reset or in software standby mode.
• Modes 4 to 6
The input/output direction specification by PDDDR is ignored, and port D is automatically
designated for data I/O.
• Mode 7
Setting a PDDDR bit to 1 makes the corresponding port D pin an output port, while clearing
the bit to 0 makes the pin an input port.
492
Abbreviation
PDDDR
PDDR
PORTD
PDPCR
6
5
4
0
0
0
W
W
W
R/W
Initial Value
W
H'00
R/W
H'00
R
Undefined
R/W
H'00
3
2
0
0
W
W
Address*
H'FE3C
H'FF0C
H'FFBC
H'FE43
1
0
0
0
W
W
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