Table of Contents
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Section
1.3.2 Pin Functions in 18
Each Operating Mode
1.3.3 Pin Functions
2.1.1 Features
2.8.5 Bus-Released
State
2.8.6 Power-Down
State
3.2.2 System Control
Register (SYSCR)
3.2.3 Pin Function
Control Register
(PFCR)
3.5 Address Map in
Each Operating Mode
4.1.3 Exception Vector
Table
4.2.5 State of On-Chip
Supporting Modules
after Reset Release
2
Page
Item
22 to 26
Table 1-2 (b) Pin Functions
in Each Operating Mode
(H8S/2633R)
27 to 31
Table 1-2 (c) Pin Functions
in Each Operating Mode
(H8S/2695)
32
38 to 43
Table 1-3 (b) Pin Functions
(H8S/2633R)
44 to 48
Table 1-3 (c) Pin Functions
(H8S/2695)
50
• High-speed operation
90
90
98
Bit 2—Manual Reset Selection
Bit (MRESE)
Bit 0—RAM Enable (RAME)
100
Bit 5—BUZZ Output Enable
(BUZZE)
Bit 4—LCAS Output Pin
Selection Bit (LCASS)
103
104
Figure 3-1 Memory Map in
Each Operating Mode in the
H8S/2633, H8S/2633R
107
Figure 3-4 Memory Map in
Each Operating Mode in the
H8S/2695
111
Table 4-2 Exception Vector
Table
115
Description
Note * added to FEW pin
Newly added
Description added
Newly added
Description added
Note * added
Description added
Notes *1 and *2 added
Note * added
Description added
16 kbytes amended to 16
Mbytes
Address map for H8S/2633R
operating modes newly
added
Newly added
Note *3 amended
Note * added
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