Renesas H8S/2633 Series Hardware Manual page 16

Section
15.2.2 Timer
Control/Status Register
(TCSR)
15.2.3 Reset
Control/Status Register
(RSTCSR)
15.2.4 Pin Function
Control Register
(PFCR)
15.3.3 Timing of
Setting Overflow Flag
(OVF)
15.5.5 Internal Reset
in Watchdog Timer
Mode
15.5.6 OVF Flag
Clearing in Interval
Timer Mode
Section 16 Serial
Communication
Interface (SCI, IrDA)
(The H8S/2695 is not
equipped with an IrDA
function)
16.2.7 Serial Status
Register (SSR)
8
Page Item
677 WDT1 Mode Select
WDT0 TCSR Bit 4—Reserve
bit
WDT1 TCSR Bit 4—Prescaler
Select (PSS)
678 Bits 2 to 0—Clock Select 2 to 0
(CKS2 to CKS0)
679 WDT1 Input Clock Select
680 Bit 7—Watchdog Overflow Flag
(WOVF)
681
Bit 5—BUZZ Output Enable
(BUZZE)
686
689
690
691
706 Bit 7—Transmit Data Register
Empty (TDRE)
707 Bit 6—Receive Data Register
Full (RDRF)
709 Bit 2—Transmit End (TEND)
Description
Note * added
Note added
Note *1 added
TCSR amended to RSTCSR
in bit table description
Note * added to bit table
Note added
Note * added
Description amended
Newly added
Title amended
Note * added