Renesas H8S/2633 Series Hardware Manual page 583

Bit 7 Bit 6 Bit 5 Bit 4
Channel IOD3 IOD2 IOD1 IOD0 Description
0 0 0
1
1 0
1
Notes: *1 When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and ø/1 is used as the TCNT1
count clock, this setting is invalid and input capture is not generated.
*2 When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
0 0 TGR0D is Output disabled
output
1
compare
0
1
register*
1
0 0
1
1 0
1
0 0 TGR0D is
input
1
capture
*
1
register*
* *
Initial output is 0 0 output at compare match
output
1 output at compare match
2
Toggle output at compare
match
Output disabled
Initial output is 1 0 output at compare match
output
1 output at compare match
Toggle output at compare
match
Capture input Input capture at rising edge
source is
Input capture at falling edge
TIOCD0 pin
Input capture at both edges
2
Capture input Input capture at TCNT1
source is channel count-up/count-down*
1/count clock
(Initial value)
1
*: Don't care
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