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Start condition issuance
SCL
(master output)
SCL
(slave output)
SDA
(master output)
SDA
(slave output)
RDRF
IRIC
ICDRS
ICDRR
User processing
Figure 18-14 Example of Slave Receive Mode Operation Timing (1)
1
2
3
4
Bit 7
Bit 6
Bit 5
Bit 4
Slave address
(MLS = ACKB = 0)
5
6
7
8
Bit 3
Bit 2
Bit 1
Bit 0
R/W
[5] ICDR read
9
1
2
Bit 7
Bit 6
Data 1
[4]
A
Interrupt
request
generation
Address + R/W
Address + R/W
[5] IRIC clearance
839
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