Table of Contents
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Section
17.1.1 Features
17.2.2 Serial Status
Register (SSR)
17.3.5 Clock
17.3.6 Data Transfer
Operations
17.4 Usage Notes
2
Section 18 I
C Bus
Interface [Option]
(This function is not
available in the
H8S/2695)
2
18.2.4 I
C Bus Mode
Register (ICMR)
18.3.2 Initial Setting
18.3.3 Master
Transmit Operation
18.3.4 Master Receive
Operation
18.3.8 Operation
Using the DTC
10
Page
Item
• Three interrupt sources
767
775
785
Table 17-5 Examples of Bit
Rate B (bit/s) for Various BRR
Settings
786
Table 17-6 Examples of
BRR Settings for Bit Rate B
(bit/s)
Table 17-7 Maximum Bit Rate
at Various Frequencies (Smart
Card Interface Mode)
793, 794
Data Transfer Operation by
DMAC or DTC
797, 798
Retransfer Operations (Except
Block Transfer Mode)
799
811
Bits 5 to 3—Serial Clock Select
(CKS2 to CKS0)
815
Bit 3—Acknowledge Bit
Judgement Selection (ACKE)
2
816 to 818 Bit 1—I
C Bus Interface
Interrupt Request Flag (IRIC)
2
820, 821
Bit 5—I
C Bus Interface
Continuous
Transmission/Reception
Interrupt Request Flag (IRTR)
829
829 to 832
833 to 837
843
Table 18-5 Examples of
Operation Using the DTC
Description
Note * added
Note * added to Bit 2 table
28 MHz bit rate added
Note * added
Title amended
Transfer rate ø = 28 MHz
portion added
Note * added
Newly added
Replaced
Note * added
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