Register Configuration - Renesas H8S/2633 Series Hardware Manual

Name Symbol
WAIT
Wait
BREQ
Bus request
BACK
Bus request
acknowledge
BREQO
Bus request output
7.1.4

Register Configuration

Table 7-2 summarizes the registers of the bus controller.
Table 7-2 Bus Controller Registers
Name
Bus width control register
Access state control register
Wait control register H
Wait control register L
Bus control register H
Bus control register L
Pin function control register
Memory control register
DRAM control register
Refresh timer counter
Refresh time constant register
Notes: *1 Lower 16 bits of the address.
*2 Determined by the MCU operating mode.
*3 This function is not available in the H8S/2695.
I/O Function
Input Wait request signal when accessing external 3-state
access space.
Input Request signal that releases bus to external device.
Output Acknowledge signal indicating that bus has been
released.
Output External bus request signal used when internal bus
master accesses external space when external bus is
released.
Abbreviation R/W
ABWCR R/W
ASTCR R/W
WCRH R/W
WCRL R/W
BCRH R/W
BCRL R/W
PFCR R/W
3
MCR *
R/W
3
DRAMCR *
R/W
3
RTCNT *
R/W
3
RTCOR *
R/W
Initial Value
Power-On Manual
Reset Reset
2
H'FF/H'00 *
Retained
H'FF Retained
H'FF Retained
H'FF Retained
H'D0 Retained
H'08 Retained
H'0D/H'00 Retained
H'00 Retained
H'00 Retained
H'00 Retained
H'FF Retained
1
Address *
H'FED0
H'FED1
H'FED2
H'FED3
H'FED4
H'FED5
H'FDEB
H'FED6
H'FED7
H'FED8
H'FED9
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