Table of Contents
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Section
Section 6 PC Break
Controller (PBC)
(This function is not
available in the
H8S/2695)
7.1 Overview
7.1.1 Features
7.1.2 Block Diagram
7.1.3 Pin
Configuration
7.1.4 Register
Configuration
7.2.4 Bus Control
Register H (BCRH)
7.2.5 Bus Control
Register L (BCRL)
7.2.6 Pin Function
Control Register
(PFCR)
7.2.7 Memory Control
Register (MCR)
7.2.8 DRAM Control
Register (DRAMCR)
7.2.9 Refresh Timer
Counter (RTCNT)
7.2.10 Refresh Time
Constant Register
(RTCOR)
7.3 Overview of Bus
Control
7.3.2 Bus
Specifications
4
Page
Item
153
165
165, 166
167
Figure 7-1 Block Diagram
of Bus Controller
168
Table 7-1 Bus Controller Pins
169
Table 7-2 Bus Controller
Registers
175
177
Bits 2 to 0—RAM Type Select
(RMTS2 to RMTS0)
178
180
183
185
Bits 2 to 0—Refresh Counter
Clock Select (CKS2 to CKS0)
187
188 to 192
189
(1) Bus Width
Description
Title amended
Note * added
Note *3 added
Note * added
Self-refresh amended to
refresh control (RFSHE = 1)
Note * added
Amended from ADWCR to
ABWCR
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