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4.4
Interrupts
Interrupt exception handling can be requested by nine external sources (NMI, IRQ7 to IRQ0) and
72 internal sources in the on-chip supporting modules. Figure 4-4 classifies the interrupt sources
and the number of interrupts of each type.
The on-chip supporting modules that can request interrupts include the watchdog timer (WDT),
16-bit timer-pulse unit (TPU), 8-bit timer * , serial communication interface (SCI), data transfer
controller (DTC) * , DMA controller (DMAC) * , PC break controller (PBC) * , A/D converter, and
2
C bus interface (IIC) * . Each interrupt source has a separate vector address.
I
NMI is the highest-priority interrupt. Interrupts are controlled by the interrupt controller. The
interrupt controller has two interrupt control modes and can assign interrupts other than NMI to
eight priority/mask levels to enable multiplexed interrupt control.
For details of interrupts, see section 5, Interrupt Controller.
Note: * This function is not available in the H8S/2695.
Interrupts
Numbers in parentheses are the numbers of interrupt sources.
Notes:
*1 When the watchdog timer is used as an interval timer, it generates
*2 When refresh timer is used as an interval time, an interrupt request
*3 This function is not available in the H8S/2695.
Figure 4-4 Interrupt Sources and Number of Interrupts
External
interrupts
Internal
interrupts
an interrupt request at each counter overflow.
is generated by compare match.
NMI (1)
IRQ7 to IRQ0 (8)
*1
WDT
(2)
*2 *3
Refresh timer
(1)
TPU (26)
*3
8-bit timer
(12)
SCI (20)
*3
DTC
(1)
*3
DMAC
(4)
*3
PBC
(1)
A/D converter (1)
*3
IIC
(4) (Option)
117
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