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13.2
Register Descriptions
13.2.1
Timer Counters 0 to 3 (TCNT0 to TCNT3)
Bit
:
15
14
Initial value
:
0
0
R/W
:
R/W
R/W
TCNT0 to TCNT3 are 8-bit readable/writable up-counters that increment on pulses generated from
an internal or external clock source. This clock source is selected by clock select bits CKS2 to
CKS0 of TCR. The CPU can read or write to TCNT0 to TCNT3 at all times.
TCNT0 and TCNT1 (TCNT2 and TCNT3) comprise a single 16-bit register, so they can be
accessed together by word transfer instruction.
TCNT0 and TCNT1 (TCNT2 and TCNT3) can be cleared by an external reset input or by a
compare match signal. Which signal is to be used for clearing is selected by clock clear bits
CCLR1 and CCLR0 of TCR.
When a timer counter overflows from H'FF to H'00, OVF in TCSR is set to 1.
TCNT0 and TCNT1 are each initialized to H'00 by a reset and in hardware standby mode.
13.2.2
Time Constant Registers A0 to A3 (TCORA0 to TCORA3)
Bit
:
15
14
Initial value
:
1
1
R/W
:
R/W
R/W
TCORA0 to TCORA3 are 8-bit readable/writable registers. TCORA0 and TCORA1 (TCORA2
and TCORA3) comprise a single 16-bit register so they can be accessed together by word transfer
instruction.
TCORA is continually compared with the value in TCNT. When a match is detected, the
corresponding CMFA flag of TCSR is set. Note, however, that comparison is disabled during the
T2 state of a TCOR write cycle.
TCNT0 (TCNT2)
13
12
11
10
0
0
0
0
R/W
R/W
R/W
R/W
R/W
TCORA0 (TCORA2)
13
12
11
10
1
1
1
1
R/W
R/W
R/W
R/W
R/W
9
8
7
6
5
0
0
0
0
0
R/W
R/W
R/W
R/W
TCORA1 (TCORA3)
9
8
7
6
5
1
1
1
1
1
R/W
R/W
R/W
R/W
TCNT1 (TCNT3)
4
3
2
1
0
0
0
0
R/W
R/W
R/W
R/W
4
3
2
1
1
1
1
1
R/W
R/W
R/W
R/W
0
0
R/W
0
1
R/W
633
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