Operation In Block Transfer Mode - Renesas H8S/2633 Series Hardware Manual

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Table of Contents

Powering On: To secure the clock duty from power-on, the following switching procedure should

be followed.

[1] The initial state is port input and high impedance. Use a pull-up resistor or pull-down resistor

to fix the potential.

[2] Fix the SCK pin to the specified output level with the CKE1 bit in SCR.

[3] Set SMR and SCMR, and switch to smart card mode operation.

[4] Set the CKE0 bit in SCR to 1 to start clock output.

Operation in Block Transfer Mode

Operation in block transfer mode is the same as in SCI asynchronous mode, except for the

following points. For details, see section 16.3.2, Operation in Asynchronous Mode.

(1) Data Format

The data format is 8 bits with parity. There is no stop bit, but there is a 2-bit (1-bit or more in

reception) error guard time.

Also, except during transmission (with start bit, data bits, and parity bit), the transmission pins go

to the high-impedance state, so the signal lines must be fixed high with a pull-up resistor.

(2) Transmit/Receive Clock

Only an internal clock generated by the on-chip baud rate generator can be used as the

transmit/receive clock. The number of basic clock periods in a 1-bit transfer interval can be set to

32, 64, 372, or 256 with bits BCP1 and BCP0. For details, see section 17.3.5, Clock.

(3) ERS (FER) Flag

As with the normal Smart Card interface, the ERS flag indicates the error signal status, but since

error signal transmission and reception is not performed, this flag is always cleared to 0.