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Section 1 Overview
1.1
Overview
The H8S/2633 Series is a series of microcomputers (MCUs: microcomputer units), built around
the H8S/2600 CPU, employing Hitachi's proprietary architecture, and equipped with peripheral
functions on-chip.
The H8S/2600 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general
registers and a concise, optimized instruction set designed for high-speed operation, and can
address a 16-Mbyte linear address space. The instruction set is upward-compatible with H8/300
and H8/300H CPU instructions at the object-code level, facilitating migration from the H8/300,
H8/300L, or H8/300H Series.
On-chip peripheral functions required for system configuration include DMA controller
2
2
(DMAC) *
, data transfer controller (DTC) *
bus masters, ROM and RAM memory, a 16-bit timer-
2
2
pulse unit (TPU), programmable pulse generator (PPG) *
, 8-bit timer *
, 14-bit PWM timer
(PWM) *
2
, watchdog timer (WDT), serial communication interface (SCI, IrDA) *
2
, A/D converter,
D/A converter *
2
, and I/O ports. It is also possible to incorporate an on-chip PC bus interface
2
(IIC) *
as an option.
1
On-chip ROM is available as 256-kbyte flash memory (F-ZTAT™ version) *
or as 256-, 128-, or
64-kbyte mask ROM. ROM is connected to the CPU via a 16-bit data bus, enabling both byte and
word data to be accessed in one state. Instruction fetching has been speeded up, and processing
speed increased.
Four operating modes, modes 4 to 7, are provided, and there is a choice of single-chip mode or
external expansion mode.
The features of the H8S/2633 Series are shown in table 1-1.
Notes: *1 F-ZTAT™ is a trademark of Hitachi, Ltd.
*2 This function is not available in the H8S/2695.
1
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