Table of Contents
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2.9
Basic Timing.....................................................................................................................
2.9.1
Overview .............................................................................................................
2.9.2
On-Chip Memory (ROM, RAM) ........................................................................
2.9.3
On-Chip Supporting Module Access Timing......................................................
2.9.4
External Address Space Access Timing..............................................................
2.10 Usage Note .......................................................................................................................
2.10.1 TAS Instruction ...................................................................................................
Section 3
3.1
Overview...........................................................................................................................
3.1.1
Operating Mode Selection...................................................................................
3.1.2
Register Configuration ........................................................................................
3.2
Register Descriptions........................................................................................................
3.2.1
Mode Control Register (MDCR).........................................................................
3.2.2
System Control Register (SYSCR) .....................................................................
3.2.3
Pin Function Control Register (PFCR) ...............................................................
3.3
Operating Mode Descriptions........................................................................................... 102
3.3.1
Mode 4................................................................................................................. 102
3.3.2
Mode 5................................................................................................................. 102
3.3.3
Mode 6................................................................................................................. 102
3.3.4
Mode 7................................................................................................................. 102
3.4
Pin Functions in Each Operating Mode............................................................................ 103
3.5
Address Map in Each Operating Mode............................................................................. 103
Section 4
4.1
Overview........................................................................................................................... 109
4.1.1
Exception Handling Types and Priority .............................................................. 109
4.1.2
Exception Handling Operation ............................................................................ 110
4.1.3
Exception Vector Table....................................................................................... 110
4.2
Reset ................................................................................................................................. 112
4.2.1
Overview ............................................................................................................. 112
4.2.2
Types of Reset ..................................................................................................... 112
4.2.3
Reset Sequence.................................................................................................... 113
4.2.4
Interrupts after Reset ........................................................................................... 115
4.2.5
State of On-Chip Supporting Modules after Reset Release ................................ 115
4.3
Traces ............................................................................................................................... 116
4.4
Interrupts........................................................................................................................... 117
4.5
Trap Instruction ................................................................................................................ 118
4.6
Stack Status after Exception Handling ............................................................................. 119
4.7
Notes on Use of the Stack................................................................................................. 120
Section 5
5.1
Overview........................................................................................................................... 121
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