Renesas H8S/2633 Series Hardware Manual page 285

(4) Notes
The setting of the ICIS0 and ICIS1 bits is invalid when accessing the DRAM space. For example,
if the 2nd of successive reads of different areas is a DRAM access, only the T
not the T cycle. Figure 7-36 shows the timing. Note, however, that ICIS0 and ICIS1 settings are
1
valid in burst access in RAS down mode, and an idle cycle is inserted. Figure 7-37 (a) and (b)
shows the timing.
Address bus
Data bus
Figure 7-36 Example of DRAM Access after External Read
T
p
EXTAL
Address
RD
RAS
CAS, LCAS
Data bus
Figure 7-37 (a) Example Idle Cycle Operation in RAS Down Mode (ICIS1=1)
External read
T T
1 2
ø
RD
DRAM space read
T T T
r c1 c2
DRAM space read
T T T T
3 p r
External read
T T T T
1 1 2
cycle is inserted,
P
T
c1 c2
DRAM space read
T T T
3 c1 c1 c2
Idle cycle
231