Pulse-Width Modulation (Pwm) Mode - Renesas M16C Series User Manual

M30240 Group

1.2.21.4 Pulse-width modulation (PWM) mode

In this mode, the timer outputs pulses of a given width in succession (See Table 1.22 ). In this mode,
the counter functions as either a 16-bit pulse-width modulator or an 8-bit pulse-width modulator. Figure
1.67 shows an example of how a 16-bit pulse-width modulator operates. Figure 1.68 shows the Timer
Ai mode register in pulse-width modulation mode. Figure 1.69 shows the example of how an 8-bit
pulse width modulator operates.
Table 1.22: Timer specifications in pulse-width modulation mode
Item
Count source
Count operation
16-bit PWM
8-bit PWM
Count start condition
Count stop condition
Interrupt request
generation timing
TAi pin function
IN
TAi pin function
OUT
Read from timer
Write to timer
Condition
Count source
TA i
IN
input signal
PWM pulse output
from TA
Timer Ai interrupt
request bit
f : Frequency of count source
i
(f
Note: n = 0000
Figure 1.67: Example of how a 16-bit pulse-width modulator operates
Rev.1.00 Sep 24, 2003 Page 74 of 360
f1, f8, f32
•The timer counts down (operating as an 8-bit or a 16-bit pulse-width modulator)
•The timer reloads a new count at a rising edge of PWM pulse and continues counting
• The timer is not affected by a trigger that occurs when counting
•High level width n / f n: Set value
i
16
•Cycle time (2 -1) / f
i
•High level width n (m+1) /f
8
•Cycle time (2 -1) (m+1) /f
•External trigger is input
•The timer overflows
•The count start flag is set (= 1)
•The count start flag is reset (= 0)
PWM pulse goes "L"
Programmable I/O port or trigger input
Pulse output
When Timer Ai register is read, it indicates an indeterminate value
•When counting is stopped and a value is written to Timer Ai register, it is written to both
reload register and the counter
•When counting in progress and a value is written to Timer A register, it is written to only
reload register to be transferred to the counter at next reload timer.
: Reload register = 0003 , when external trigger
16
(rising edge of TA iIN pin input signal) is selected
"H"
pin
"L"
"H"
pin
iOUT
"L"
"1"
"0"
, f , f )
1 8 32
Cleared to "0" when interrupt request is accepted, or cleared by software
to FFFE
16 16
Specification
fixed
n: values set to timer Ai register's high-order address
i
m: values set to timer Ai register's low-order address
i
16
1 / f (2 – 1)
X
i
Trigger is not generated by this signal
1 / f n
X
i
Timer A