Usart Status & Interrupt Flag Register - Usrsifr - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
Bits Field
[4] PEIE
[3] OEIE
[2] TXCIE
[1] TXDEIE
[0] RXDRIE
USART Status & Interrupt Flag Register – USRSIFR
This register contains the corresponding USART status.
Offset : 0x010
Reset value: 0x0000_0180
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
TXDE
Type/Reset RO 1 WC
Rev. 1.10
Descriptions
Parity Error Interrupt Enable
0: Disable interrupt
1: Enable interrupt
If this bit is set to 1, an interrupt is generated when the PEI bit is set in the
USRSIFR register.
Overrun Error Interrupt Enable
0: Disable interrupt
1: Enable interrupt
If this bit is set to 1, an interrupt is generated when the OEI bit is set in the
USRSIFR register.
Transmit Complete Interrupt Enable
0: Disable interrupt
1: Enable interrupt
If this bit is set to 1, an interrupt is generated when the TXC bit is set in the
USRSIFR register.
Transmit Data Empty Interrupt Enable
0: Disable interrupt
1: Enable interrupt
If this bit is set to 1, an interrupt is generated when the TXDE bit is set in the
USRSIFR register.
Receive Data Ready Interrupt Enable
0: Disable interrupt
1: Enable interrupt
If this bit is set to 1, an interrupt is generated when the RXDR bit is set in the
USRSIFR register.
30 29 28
22 21 20
14 13 12
Reserved
6 5 4
RXTOF RXDR BII
0 RO 0 WC
447 of 590
27 26
Reserved
19 18
Reserved
11 10
CTSS CTSC
RO 0 WC 0 WC
3 2
FEI PEI
0 WC 0 WC 0 WC
25 24
17 16
9 8
RSADD TXC
0 RO 1
1 0
OEI RXDNE
0 RO 0
November 28, 2018