Spi Fifo Time Out Counter Register - Spiftocr - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230
SPI FIFO Time Out Counter Register – SPIFTOCR
This register stores the SPI RX FIFO time out counter value.
Offset: 0x020
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset RW 0 RW
7
Type/Reset RW 0 RW
Bits Field
[15:0] TOC
Rev. 1.10
30 29 28
22 21 20
14 13 12
0 RW 0 RW
6 5 4
0 RW 0 RW
Descriptions
Time Out Counter
The time out counter starts to count from 0 after the SPI RX FIFO receives a data,
and reset the counter value once the data is read from the SPIDR register by
software or another new data is received. If the FIFO does not receive new data
or the software does not read data from the SPIDR register the time out counter
value will continuously increase. When the time out counter value is equal to the
TOC setting value, the TO flag in the SPISR register will be set and an interrupt will
be generated if the TOIEN bit in the SPIIEN register is set. The time out counter
will be stopped when the RX FIFO is empty. The SPI FIFO time out function can
be disabled by setting the TOC field to zero. The time out counter is driven by the
system APB clock, named f
PCLK
325 of 366
27 26
Reserved
19 18
Reserved
11 10
TOC
0 RW 0 RW 0 RW
3 2
TOC
0 RW 0 RW 0 RW
.
25 24
17 16
9 8
0 RW 0
1 0
0 RW 0
November 09, 2018