I 2 C Interrupt Enable Register - I2Cier - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
I 2 C Interrupt Enable Register – I2CIER
This register specifies the corresponding I
Offset: 0x004
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Type/Reset
Bits Field
[18] RXBFIE
[17] TXDEIE
[16] RXDNEIE
[11] TOUTIE
[10] BUSERRIE
[9] RXNACKIE
Rev. 1.10
2 C interrupt enable bits.
30 29 28
22 21 20
Reserved
14 13 12
Reserved
6 5 4
Reserved
Descriptions
RX Buffer Full Interrupt Enable Bit
0: Interrupt disabled
1: Interrupt enabled
When the I2CEN bit in the I2CCR register is cleared to 0, this bit is cleared to 0 by
hardware.
Data Register Empty Interrupt Enable Bit in Transmitter Mode
0: Interrupt disabled
1: Interrupt enabled
When the I2CEN bit in the I2CCR register is cleared to 0, this bit is cleared to 0 by
hardware.
Data Register Not Empty Interrupt Enable Bit in Received Mode
0: Interrupt disabled
1: Interrupt enabled
When the I2CEN bit in the I2CCR register is cleared to 0, this bit is cleared to 0 by
hardware.
Timeout Interrupt Enable Bit
0: Interrupt disabled
1: Interrupt enabled
When the I2CEN bit in the I2CCR register is cleared to 0, this bit is cleared to 0 by
hardware.
Bus Error Interrupt Enable Bit
0: Interrupt disabled
1: Interrupt enabled
When the I2CEN bit in the I2CCR register is cleared to 0, this bit is cleared to 0 by
hardware.
Received Not Acknowledge Interrupt Enable Bit
0: Interrupt disabled
1: Interrupt enabled
When the I2CEN bit in the I2CCR register is cleared to 0, this bit is cleared to 0 by
hardware.
400 of 590
27 26
Reserved
19 18
RXBFIE TXDEIE
RW 0 RW
11 10
TOUTIE BUSERRIE RXNACKIE ARBLOSIE
RW 0 RW 0 RW
3 2
GCSIE ADRSIE
RW 0 RW 0 RW
25 24
17 16
RXDNEIE
0 RW 0
9 8
0 RW 0
1 0
STOIE STAIE
0 RW 0
November 28, 2018