Channel 0 Output Configuration Register - Ch0Ocfr - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
Bits Field
[3:0] TI3F
Channel 0 Output Configuration Register – CH0OCFR
This register specifies the channel 0 output mode configuration.
Offset: 0x040
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Reserved
Type/Reset
Bits Field
[5] CH0IMAE
Rev. 1.10
Descriptions
Channel 3 Input Source TI3 Filter Setting
These bits define the frequency divided ratio used to sample the TI3 signal. The
Digital filter in the GPTM is an N-event counter where N is defined as how many
valid transitions are nevessary to output a filtered signal.
0000: No filter, sampling is done at f
0001: f = f , N = 2
SAMPLING CLKIN
0010: f = f , N = 4
SAMPLING CLKIN
0011: f = f , N = 8
SAMPLING CLKIN
0100: f = f / 2, N = 6
SAMPLING DTS
0101: f = f / 2, N = 8
SAMPLING DTS
0110: f = f / 4, N = 6
SAMPLING DTS
0111: f = f / 4, N = 8
SAMPLING DTS
1000: f = f / 8, N = 6
SAMPLING DTS
1001: f = f / 8, N = 8
SAMPLING DTS
1010: f = f / 16, N = 5
SAMPLING DTS
1011: f = f / 16, N = 6
SAMPLING DTS
1100: f = f / 16, N = 8
SAMPLING DTS
1101: f = f / 32, N = 5
SAMPLING DTS
1110: f = f / 32, N = 6
SAMPLING DTS
1111: f = f / 32, N = 8
SAMPLING DTS
30 29 28
22 21 20
14 13 12
Reserved
6 5 4
CH0IMAE CH0PRE
RW 0 RW
Descriptions
Channel 0 Immediate Active Enable
0: No action
1: Single pulse Immediate Active Mode is enabled
The CH0OREF will be forced to the compare matched level immediately after an
available trigger event occurs irrespective of the result of the comparison between
the CNTR and the CH0CCR values.
The effective duration ends automatically at the next overflow or underflow event.
Note: The CH0IMAE bit is available only if the channel 0 is configured to be operated
in the PWM mode 1 or the PWM mode 2.
263 of 590
DTS
27 26
Reserved
19 18
Reserved
11 10
3 2
REF0CE CH0OM[2:0]
0 RW 0 RW 0 RW
25 24
17 16
9 8
CH0OM[3]
RW 0
1 0
0 RW 0
November 28, 2018