32-Bit Arm
®
Cortex
®
-M0+ MCU
HT32F54231/HT32F54241/HT32F54243/HT32F54253
4
4
Flash Memory Controller (FMC)
Introduction
The Flash Memory Controller, FMC, provides all the necessary functions and pre-fetch buffer for
the embedded on-chip Flash memory. The figure below shows the block diagram of FMC which
includes programming interface, control register, pre-fetch buffer and access interface. Since the
access speed of the Flash memory is slower than the CPU, a wide access interface with a pre-fetch
buffer is provided to the Flash memory in order to reduce the CPU waiting time which will cause
CPU instruction execution delay. The Flash memory word programming/page erase functions are
also provided for instruction/data storage.
AHB
Peripheral
Bus
Figure 7. Flash Memory Controller Block Diagram
Features
Up to 128 KB of on-chip Flash memory for storing instruction/data and option bytes
▆
●
128 KB (instruction/data + Option Byte) for the HT32F54253
●
64 KB (instruction/data + Option Byte) for the HT32F54241 and HT32F54243
●
32 KB (instruction/data + Option Byte) for the HT32F54231
Page size of 1 KB, totally up to 128 pages depending on the main Flash size
▆
Wide access interface with a pre-fetch buffer to reduce instruction gaps
▆
Page erase and mass erase capability
▆
32-bit word programming
▆
Interrupt function to indicate end of Flash memory operations or an error occurrence
▆
Flash read protection to prevent illegal code/data access
▆
Page erase/program protection to prevent unexpected operations
▆
Rev. 1.00
Flash Memory Controller
Control Register
Pre-fetch Buffer
Programming
43 of 576
Information
Wait State
Control
Addressing
Main Flash
Data
Control
January 28, 2022
Flash
Block
Memory
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